Paste Verilog. Supports: gate primitives (and/or/not/nand/nor/xor/xnor), continuous assigns (assign y = a & b;, also | ^ ~ and negated combos), bus widths ([3:0]), aliases, constants (1'b0/1'b1), and simple sequential always @(posedge clk) blocks for DFFs, counters, shift registers, enables, resets, and small if/else FSMs.