{
  "format": "fpgalib",
  "version": 1,
  "created": "2026-05-25",
  "metadata": {
    "name": "Standard sub-circuits",
    "description": "Reusable half-adder, full-adder, and parameterized n-bit register blocks.",
    "author": "Gerty"
  },
  "subcircuits": [
    {
      "id": "half_adder",
      "name": "half_adder",
      "version": 1,
      "ports": {
        "inputs": [
          { "name": "a", "componentId": "ha_a", "pin": 0 },
          { "name": "b", "componentId": "ha_b", "pin": 0 }
        ],
        "outputs": [
          { "name": "sum", "componentId": "ha_sum", "pin": 0 },
          { "name": "carry", "componentId": "ha_carry", "pin": 0 }
        ]
      },
      "circuit": {
        "v": 3,
        "name": "half_adder",
        "meta": { "pinnedTraces": [] },
        "components": [
          { "id": "ha_a", "type": "input", "x": 60, "y": 80, "label": "a", "props": { "value": false } },
          { "id": "ha_b", "type": "input", "x": 60, "y": 160, "label": "b", "props": { "value": false } },
          { "id": "ha_xor", "type": "xor", "x": 190, "y": 80, "label": "sum_xor" },
          { "id": "ha_and", "type": "and", "x": 190, "y": 170, "label": "carry_and" },
          { "id": "ha_sum", "type": "output", "x": 330, "y": 95, "label": "sum" },
          { "id": "ha_carry", "type": "output", "x": 330, "y": 185, "label": "carry" }
        ],
        "wires": [
          { "from": "ha_a.out0", "to": "ha_xor.in0" },
          { "from": "ha_b.out0", "to": "ha_xor.in1" },
          { "from": "ha_xor.out0", "to": "ha_sum.in0" },
          { "from": "ha_a.out0", "to": "ha_and.in0" },
          { "from": "ha_b.out0", "to": "ha_and.in1" },
          { "from": "ha_and.out0", "to": "ha_carry.in0" }
        ]
      }
    },
    {
      "id": "full_adder",
      "name": "full_adder",
      "version": 1,
      "ports": {
        "inputs": [
          { "name": "a", "componentId": "fa_a", "pin": 0 },
          { "name": "b", "componentId": "fa_b", "pin": 0 },
          { "name": "cin", "componentId": "fa_cin", "pin": 0 }
        ],
        "outputs": [
          { "name": "sum", "componentId": "fa_sum", "pin": 0 },
          { "name": "cout", "componentId": "fa_cout", "pin": 0 }
        ]
      },
      "circuit": {
        "v": 3,
        "name": "full_adder",
        "meta": { "pinnedTraces": [] },
        "components": [
          { "id": "fa_a", "type": "input", "x": 50, "y": 80, "label": "a", "props": { "value": false } },
          { "id": "fa_b", "type": "input", "x": 50, "y": 150, "label": "b", "props": { "value": false } },
          { "id": "fa_cin", "type": "input", "x": 50, "y": 220, "label": "cin", "props": { "value": false } },
          { "id": "fa_ha1", "type": "subcircuit", "x": 210, "y": 95, "label": "half_adder A+B", "props": { "subcircuitId": "half_adder", "subcircuitName": "half_adder", "ports": { "inputs": [ { "name": "a", "componentId": "ha_a", "pin": 0 }, { "name": "b", "componentId": "ha_b", "pin": 0 } ], "outputs": [ { "name": "sum", "componentId": "ha_sum", "pin": 0 }, { "name": "carry", "componentId": "ha_carry", "pin": 0 } ] } } },
          { "id": "fa_ha2", "type": "subcircuit", "x": 410, "y": 150, "label": "half_adder +Cin", "props": { "subcircuitId": "half_adder", "subcircuitName": "half_adder", "ports": { "inputs": [ { "name": "a", "componentId": "ha_a", "pin": 0 }, { "name": "b", "componentId": "ha_b", "pin": 0 } ], "outputs": [ { "name": "sum", "componentId": "ha_sum", "pin": 0 }, { "name": "carry", "componentId": "ha_carry", "pin": 0 } ] } } },
          { "id": "fa_or", "type": "or", "x": 610, "y": 250, "label": "carry_or" },
          { "id": "fa_sum", "type": "output", "x": 650, "y": 165, "label": "sum" },
          { "id": "fa_cout", "type": "output", "x": 760, "y": 260, "label": "cout" }
        ],
        "wires": [
          { "from": "fa_a.out0", "to": "fa_ha1.in0" },
          { "from": "fa_b.out0", "to": "fa_ha1.in1" },
          { "from": "fa_ha1.out0", "to": "fa_ha2.in0" },
          { "from": "fa_cin.out0", "to": "fa_ha2.in1" },
          { "from": "fa_ha2.out0", "to": "fa_sum.in0" },
          { "from": "fa_ha1.out1", "to": "fa_or.in0" },
          { "from": "fa_ha2.out1", "to": "fa_or.in1" },
          { "from": "fa_or.out0", "to": "fa_cout.in0" }
        ]
      }
    },
    {
      "id": "nbit_register",
      "name": "nbit_register",
      "version": 1,
      "param": { "name": "W", "default": 4, "min": 1, "max": 64 },
      "ports": {
        "inputs": [
          { "name": "d", "componentId": "nr_d", "pin": 0, "bits": "W" },
          { "name": "clk", "componentId": "nr_clk", "pin": 0 },
          { "name": "rst", "componentId": "nr_rst", "pin": 0 }
        ],
        "outputs": [
          { "name": "q", "componentId": "nr_q", "pin": 0, "bits": "W" }
        ]
      },
      "circuit": {
        "v": 3,
        "name": "nbit_register",
        "meta": { "pinnedTraces": [] },
        "components": [
          { "id": "nr_d", "type": "input", "x": 50, "y": 80, "label": "d", "props": { "bits": "W", "value": false } },
          { "id": "nr_clk", "type": "input", "x": 50, "y": 250, "label": "clk", "props": { "value": false } },
          { "id": "nr_rst", "type": "input", "x": 50, "y": 320, "label": "rst", "props": { "value": false } },
          { "id": "nr_reg", "type": "register", "x": 230, "y": 90, "label": "reg", "props": { "bits": "W" } },
          { "id": "nr_q", "type": "output", "x": 430, "y": 100, "label": "q", "props": { "bits": "W" } }
        ],
        "wires": [
          { "from": "nr_d.out0", "to": "nr_reg.in0" },
          { "from": "nr_d.out1", "to": "nr_reg.in1" },
          { "from": "nr_d.out2", "to": "nr_reg.in2" },
          { "from": "nr_d.out3", "to": "nr_reg.in3" },
          { "from": "nr_d.out4", "to": "nr_reg.in4" },
          { "from": "nr_d.out5", "to": "nr_reg.in5" },
          { "from": "nr_d.out6", "to": "nr_reg.in6" },
          { "from": "nr_d.out7", "to": "nr_reg.in7" },
          { "from": "nr_clk.out0", "to": "nr_reg.inW" },
          { "from": "nr_rst.out0", "to": "nr_reg.inW+1" },
          { "from": "nr_reg.out0", "to": "nr_q.in0" },
          { "from": "nr_reg.out1", "to": "nr_q.in1" },
          { "from": "nr_reg.out2", "to": "nr_q.in2" },
          { "from": "nr_reg.out3", "to": "nr_q.in3" },
          { "from": "nr_reg.out4", "to": "nr_q.in4" },
          { "from": "nr_reg.out5", "to": "nr_q.in5" },
          { "from": "nr_reg.out6", "to": "nr_q.in6" },
          { "from": "nr_reg.out7", "to": "nr_q.in7" }
        ]
      }
    }
  ]
}